march 20 01 s i 34 4 2 dv n -channel logic level enhancement mode field effect transistor general description features ____________________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise note symbol parameter s i 34 42 d v v dss drain-source voltage 20 v v gss gate-source voltage - continuous 8 v i d drain current - continuous (note 1a) 4.1 a - pulsed 15 p d maximum power dissipation (note 1a) 1.6 w (note 1b) 1 (note 1c) 0.8 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 30 c/w s i 3 44 2 dv r e v . a 3 5 6 4 1 2 these n -channel logic level enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is tailored to minimize on-state resistance. these devices are particularly suited for low voltage applications in notebook computers, portable phones, pcmica cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 4.1 a, 20 v. ?r ds(on ) = 0.06 w @ v gs = 4.5 v r ds(on ) = 0.075 w @ v gs =2.7 v . proprietary supersot tm -6 package design using copper lead frame for superior thermal and electrical capabilities. high density cell design for extremely low r ds(on) . exceptional on-resistance and maximum dc current capability. ? 200 1 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 20 v i dss zero gate voltage drain current v ds = 16 v , v gs = 0 v 1 a t j = 55 o c 10 a i gssf gate - body leakage, forward v gs = 8 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -8 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 0.4 0.7 1 v t j = 125 o c 0.3 0.5 0.8 r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 4.1 a 0.039 0.06 w t j = 125 o c 0.06 0.11 v gs = 2.7 v, i d = 3.6 a 0.05 0.075 i d (on) on-state drain current v gs = 4.5 v, v ds = 5 v 15 a g fs forward transconductance v ds = 4.5 v, i d = 4.1 a 12 s dynamic characteristics c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1.0 mhz 365 pf c oss output capacitance 230 pf c rss reverse transfer capacitance 95 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = 5 v, i d = 1 a, v gen = 4.5 v, r gen = 6 w 9 17 ns t r turn - on rise time 25 45 ns t d(off) turn - off delay time 28 50 ns t f turn - off fall time 8 15 ns q g total gate charge v ds = 10 v, i d = 4.1 a, v gs = 4.5 v 10 14 nc q gs gate-source charge 1 nc q gd gate-drain charge 3.3 nc s i 34 4 2 dv rev. a
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units drain-source diode characteristics i s continuous source diode current 1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.3 a (note 2 ) 0.75 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 78 o c/w when mounted on a 1 in 2 pad of 2oz copper. b. 125 o c/w when mounted on a 0.01 in 2 pad of 2oz copper. c. 156 o c/w when mounted on a 0.003 in 2 pad of 2oz copper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. s i 34 42 dv rev. a 1a 1b 1c
s i 3 44 2 dv rev. a 0 1 2 3 0 3 6 9 12 15 v , drain-source voltage (v) i , drain-source current (a) v = 4.5v gs ds d 1.5v 2.0v 2.7v 3.0v 2.5v 0 3 6 9 12 15 0.5 1 1.5 2 2.5 i , drain current (a) drain-source on-resistance d r , normalized ds(on) v =2.0v gs 4.5v 2.5v 3.5v 2.7v 3.0v figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . typical electrical characteristics -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 1.8 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = 4.5v gs i = 4.1a d 0 3 6 9 12 15 0 0.5 1 1.5 2 2.5 i , drain current (a) drain-source on-resistance v = 4.5v gs t = 125c j 25c -55c d r , normalized ds(on) figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with drain current and temperature . 0 0.5 1 1.5 2 2.5 3 0 3 6 9 12 15 v , gate to source voltage (v) i , drain current (a) 25c 125c v =- 5v ds gs d t = -55c j -50 -25 0 25 50 75 100 125 150 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 t , junction temperature (c) gate-source threshold voltage j v , normalized th i = 250a d v = v gs ds figure 5. transfer characteristics . figure 6. gate threshold variation with temperature .
si 3 44 2 d v rev. a -50 -25 0 25 50 75 100 125 150 0.92 0.96 1 1.04 1.08 1.12 t , junction temperature (c) drain-source breakdown voltage bv , normalized dss j i = 250a d 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 1 5 10 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v =0v gs sd s figure 7. breakdown voltage variation with temperature. figure 8. body diode forward voltage variation with source current and temperature . typical electrical characteristics (continued) 0 3 6 9 12 0 1 2 3 4 5 q , gate charge (nc) v , gate-source voltage (v) g gs i = 4.1a d v = 5v ds 10v 15v 0.1 0.2 0.5 1 2 5 10 20 50 100 200 300 600 1000 1500 v , drain to source voltage (v) capacitance (pf) ds f = 1 mhz v = 0v gs c oss c iss c rss g d s v dd r l v v in out v gs dut r gen figure 9. capacitance characteristics . figure 10. gate charge characteristics. figure 11. switching test circuit . figure 12. switching waveforms . 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t tt t inverted 10% p ulse width
s i 3 4 42 dv rev. a 0 2 4 6 8 10 0 5 10 15 20 25 i , drain current (a) g , transconductance (siemens) t = -55c j d fs v = 5v ds 125c 25c figure 13. transconductance variation with drain current and temperature . figure 16. maximum safe operating area . typical electrical and thermal characteristics (continued) 0 0.2 0.4 0.6 0.8 1 2 2.5 3 3.5 4 4.5 5 2oz copper mounting pad area (in ) i , steady-state drain current (a) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = 4.5v a o gs d 0 0.2 0.4 0.6 0.8 1 0 0.5 1 1.5 2 2oz copper mounting pad area (in ) steady-state power dissipation (w) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air a o 0.1 0.2 0.5 1 2 5 10 20 40 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 v , drain-source voltage (v) i , drain current (a) ds d rds(on) limit v = 4.5v single pulse r = see note 1c t = 25c gs a q ja 1s 100ms 100us dc 10ms 1ms figure 14. supersot tm -6 maximum steady-state power dissipation versus copper mounting pad area. figure 15 . maximum steady-state drain current versus copper mounting pad area. 0.00001 0.0001 0.001 0.01 0.1 1 10 100 300 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 r(t), normalized effective figure 17 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design.
? 1998 fairchild semiconductor corporation p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 8mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 0.429 7.9 ?10.9 8mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 4.00 100 0.331 +0.059/-0.000 8.4 +1.5/0 0.567 14.4 0.311 0.429 7.9 ?10.9 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed ssot-6 embossed carrier tape configuration: fi g ure 3.0 ssot-6 reel configuration: fi g ure 4.0 dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc ssot-6 (8mm) 3.23 +/-0.10 3.18 +/-0.10 8.0 +/-0.3 1.55 +/-0.05 1.125 +/-0.125 1.75 +/-0.10 6.25 min 3.50 +/-0.05 4.0 +/-0.1 4.0 +/-0.1 1.37 +/-0.10 0.255 +/-0.150 5.2 +/-0.3 0.06 +/-0.02 supersot tm -6 tape and reel data, continued july 1999, rev. c
supersot ? -6 (fs pkg code 31, 33) supersot tm -6 package dimensions september 1998, rev. a 1:1 scale 1:1 on letter size paper dimensions shown below are in: inches [millimeters] part weight per unit (gram): 0.0158 ?2000 fairchild semiconductor international
trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. pacman? pop? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher smart start? star* power? stealth? fast fastr? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? microwire? optologic? optoplanar? rev. h1 ? ? ? ?
|
